Record Details
Offloading of I/O transactions in current CPU architectures
ScholarsArchive at Oregon State University
| Field | Value |
|---|---|
| Title | Offloading of I/O transactions in current CPU architectures |
| Names |
Larsen, Steen K.
(creator) Lee, Ben (advisor) |
| Date Issued | 2015-03-05 (iso8601) |
| Note | Graduation date: 2015 |
| Abstract | I/O transactions within a computer system have evolved along with other system components (i.e., CPU, memory, video) from programmed I/O (PIO). In current mainstream systems (spanning from HPC to mobile) the I/O transactions are CPU-centric descriptor-based DMA transactions. The key benefit is that slower I/O devices can DMA write system receive traffic to system memory and DMA read system transmit data at slower device throughput relative to the CPU. With the advent of more cores in a CPU, power restrictions and latency concerns, we show this approach has limitations and based on measurements we propose alternatives to descriptor-based DMA I/O transactions. We explore and quantify performance improvement in three options: 1) iDMA: Embedded smalller core to offload DMA descriptor processing from the larger application-oriented cores, reducing latency up to 16\% and increasing bandwidth per pin up to 17%. 2) Hot-Potato: Where latency is a concern we re-visit using WC-buffers for direct I/O CPU transactions and avoiding CPU hardware changes. While keeping a specialized receive I/O device DMA engine, we reduce latency for small messages by 1.5 μs. 3) Device2Device: For applications moving data between devices, we propose how to bypass the CPU, improving latency, power, and CPU utilization. |
| Genre | Thesis/Dissertation |
| Access Condition | http://creativecommons.org/licenses/by-nc/3.0/us/ |
| Topic | CPU |
| Identifier | http://hdl.handle.net/1957/55572 |
