Record Details
Measurement and analysis of soft error vulnerability of low-voltage logic and memory circuits
ScholarsArchive at Oregon State University
| Field | Value |
|---|---|
| Title | Measurement and analysis of soft error vulnerability of low-voltage logic and memory circuits |
| Names |
Pawlowski, Robert (Robert Stephen)
(creator) Chiang, Patrick Y. (advisor) |
| Date Issued | 2014-07-14 (iso8601) |
| Note | Graduation date: 2015 |
| Abstract | Scaling the supply voltage into the sub/near-threshold domain is one of the most effective methods for improving the energy efficiency of next-generation electronic microsystems. Unfortunately, the relationship between low-voltage operation and radiation-induced soft error rate is not widely known, as little research has been previously performed and reported for soft-error susceptibility of on-chip memory and logic at very low supply voltages. This information is critical for low-voltage circuit designers, as many applications that would benefit from the energy efficiency of sub/near-threshold also require high reliability. This work first details the design and implementation of a portable soft error reference platform, specifically targeting very low-voltage operation. The circuit-level details of a TSMC 65nm test-chip design are given, along with an analysis of data from experiments performed at Los Alamos Neutron Science Center (LANSCE) and the OSU Radiation Center. Once this soft-error rate is known, error resiliency techniques must be utilized for increased processor reliability. The design and implementation of an error-resilient, near-threshold SIMD processor in an IBM 45nm SOI process will also be covered. This prototype demonstrates both increased reliability and improved throughput over a conventional SIMD pipeline while operating in near-threshold. |
| Genre | Thesis/Dissertation |
| Access Condition | http://creativecommons.org/licenses/by-nc-nd/3.0/us/ |
| Topic | Near-Threshold |
| Identifier | http://hdl.handle.net/1957/50774 |
