Record Details
Design techniques for low-power electrical and optical serial link receivers
ScholarsArchive at Oregon State University
| Field | Value |
|---|---|
| Title | Design techniques for low-power electrical and optical serial link receivers |
| Names |
Bai, Rui
(creator) Chiang, Patrick Y. (advisor) |
| Date Issued | 2014-05-28 (iso8601) |
| Note | Graduation date: 2014 |
| Abstract | As computation power continues to grow, the demand for data transfer bandwidth is also rising. This is reflected in the increasing data-rate of high-speed links. However, the increase in data-rate is sustainable only if the I/O energy efficiency improves as well. This dissertation explores several techniques to enable high-speed links with low power consumption. First, a serial link receiver with scalable supply voltage for different data-rates for optimum energy efficiency is presented. Low-voltage operation is proven to be an effective way to reduce power consumption, but it has not been widely adopted in high-speed link design due to associated design challenges. The proposed receiver uses an injection-locked ring oscillator (ILRO) for low-power clock recovery and deskewing with wide jitter-tracking bandwidth. Optical link has become increasingly attractive due to the potential to deliver high aggregated bandwidth over longer distance compared to electrical links. The next design applies the architecture presented previously to an optical receiver in a wavelength-division modulated (WDM) link. Per-channel adaptation is built into the front-end transimpedance amplifier (TIA), which usually accounts for the highest power consumption, to enable energy optimization in the presence of prevalent variation. Built-in monitoring and controlling circuits facilitates automatic adaptation of the link. Lastly, a low-power decision-feedback equalizer (DFE) using charge-based latch is presented. Designing an equalizer for low-voltage links can be particularly challenging because it usually has the highest bandwidth among all components. The proposed DFE with charge-based latch retains the low power consumption of a dynamic latch while achieving comparable speed of power-hungry current-mode logic (CML) circuits. |
| Genre | Thesis/Dissertation |
| Topic | serial-link |
| Identifier | http://hdl.handle.net/1957/49094 |
