Record Details
Methods to improve the reliability and resiliency of near/sub-threshold digital circuits
ScholarsArchive at Oregon State University
| Field | Value |
|---|---|
| Title | Methods to improve the reliability and resiliency of near/sub-threshold digital circuits |
| Names |
Crop, Joseph A.
(creator) Chiang, Patrick (advisor) |
| Date Issued | 2014-05-28 (iso8601) |
| Note | Graduation date: 2014 |
| Abstract | Energy consumption is one of the primary bottlenecks to both large and small scale modern compute platforms. Reducing the operating voltage of digital circuits to voltages where the supply voltage is near or below the threshold of the transistors has recently gained attention as a method to reduce the energy required for computations by as much as 6 times. However, when operating at near/sub-threshold voltages (where the supply voltage is near or below the threshold of the transistors), imperfections in transistor manufacturing, changes in temperature, and other difficult-to-predict factors cause wide variations in the timing of Complementary Metal-Oxide Semiconductor (CMOS) circuits due to an increased sensitivity at lower voltages. These increased variations result in poor aggregate performance and cause increased rates of error occurrence in computation. This work introduces several new methods to improve the reliability of near/sub-threshold circuits. The first is a design automation technique that is used to aid in low-voltage digital standard cell synthesis. Second, two circuit-level techniques are also introduced that aim to improve the reliability and resiliency of digital circuits by means of completion/error detection. These techniques are shown to improve speed and lower energy consumption at low overheads compared to previous methods. Most importantly, these circuit-level methods are specifically designed to operate at low voltages and can themselves tolerate variations and operation in harsh environments. Finally, a test-chip prototype designed in 65nm-CMOS demonstrates the practicality and feasibility of a proposed current sensing error detector. |
| Genre | Thesis/Dissertation |
| Access Condition | http://creativecommons.org/licenses/by/3.0/us/ |
| Topic | Electrical Engineer |
| Identifier | http://hdl.handle.net/1957/48935 |
