Record Details
Majority logic circuits
ScholarsArchive at Oregon State University
| Field | Value |
|---|---|
| Title | Majority logic circuits |
| Names |
Anand, Satish Kumar
(creator) Stone, Louis N. (advisor) |
| Date Issued | 1965-05-27 (iso8601) |
| Note | Graduation date: 1966 |
| Abstract | This thesis considers the worst-case design of transistor circuits for the realization of Majority Logic. First the meaning of Majority Logic is discussed. The requirement of an odd number of inputs for the realization of Majority Logic is justified. The usefulness of Majority Logic in synthesizing a Boolean expression is shown with an example. Next, three separate circuits for the realization of Majority Logic are considered in detail. The three circuits are designated as: (1) Variable Threshold Transistor-Resistor Logic Circuit (VTTRL) (2) Variable Threshold Logic Circuit (VTL) (3) Transistor Tunnel-diode Resistor Logic Circuit (TTDRL). The three circuits are compared for their relative advantages and disadvantages. |
| Genre | Thesis/Dissertation |
| Topic | Transistor circuits |
| Identifier | http://hdl.handle.net/1957/48158 |
