Record Details
Optimum logic design for a fast parallel multiplier
ScholarsArchive at Oregon State University
| Field | Value |
|---|---|
| Title | Optimum logic design for a fast parallel multiplier |
| Names |
Siemens, Phillip Dennis
(creator) Stone, Louis N. (advisor) |
| Date Issued | 1966-08-23 (iso8601) |
| Note | Graduation date: 1967 |
| Abstract | This thesis discusses a method of fast multiplication by parallel addition of summands. A logical element that performs this parallel addition is defined, and examples of the element realized with threshold logic are shown. Relations between the type of logical element used, and the speed and cost of the multiplier are discussed. The optimum type of logical element is defined, and two examples of a multiplier using this optimum element are discussed. By assuming some hypothetical propagation times for the various elements, a multiply time of 500 ns is predicted for an eighty-bit multiplier. |
| Genre | Thesis/Dissertation |
| Topic | Analog multipliers |
| Identifier | http://hdl.handle.net/1957/47297 |
