Record Details
High speed adaptive logic circuit for adaptive signal processing
ScholarsArchive at Oregon State University
| Field | Value |
|---|---|
| Title | High speed adaptive logic circuit for adaptive signal processing |
| Names |
Moriyasu, Hiro
(creator) Stone, Louis N. (advisor) |
| Date Issued | 1969-05-01 (iso8601) |
| Note | Graduation date: 1969 |
| Abstract | A high speed adaptive signal processing concept and several high speed adaptive logic circuit elements are presented. The adaptive signal processing system operates in a "goal" oriented mode; the system tries to optimize its characteristics to achieve a given goal in spite of unforeseen variations in the inputs, the system, or lack of detailed bits of instruction. The adaptive logic circuits presented can perform several Boolean logical operations, such as AND, OR, NAND, NOR, memory, majority as well as arithmetic operations, without changing their circuit configurations. Possible adaptive circuits utilizing tunnel diodes and transistors and higher order adaptive logic circuits are presented. As examples of high speed operations, a 16-bit shift register, a read-only memory, and an adaptive delay line are presented. What has been presented can offer possibilities for high speed adaptive data processing. |
| Genre | Thesis/Dissertation |
| Topic | Electronic digital computers -- Circuits |
| Identifier | http://hdl.handle.net/1957/46461 |
