Record Details
Distributed Logic Memory computer for process control
ScholarsArchive at Oregon State University
| Field | Value |
|---|---|
| Title | Distributed Logic Memory computer for process control |
| Names |
Smathers, John Edward
(creator) Engle, John F. (advisor) |
| Date Issued | 1968-10-16 (iso8601) |
| Note | Graduation date: 1969 |
| Abstract | An instruction set and programming examples are described for a Distributed Logic Memory computer organization. The computer is designed to take advantage of the economies of very large-scale circuit integration. In addition, the computer can grow in an orderly way. As it grows there is increased parallelism possible so that the amount of spare real time in a control application is not greatly reduced. Finally, such an organization should permit stored program control in relatively small applications where up to now control by a conventionally organized computer has been prohibitively expensive. The computer consists of a linear array of identical, small, sequential machines, or cells. The structure is similar to that of the Distributed Logic Memory originally proposed by C. Y. Lee. It was demonstrated by J. N. Sturman that the addition of sequential logic to each cell permits the memory to become a self-contained computing system. It is the purpose of this thesis to produce an application-oriented process control computer design based on the concepts of Lee and Sturman. It was found necessary to increase the length of the memory word in each cell. The ability to store instructions and data in cells is retained. Increasing the memory word length of each cell permits an expanded instruction repertoire. The low-ordered three bits of every memory word are arranged to identify a cell as one of eight possible types. A program instruction includes modifier bits which specify the types of cells on which the instruction is to operate. This facility enhances the efficiency of programs. The logic design of the cell is complete enough to permit estimating gate count per cell. An analysis of the sensitivity of gate count to changes in the instruction set is included. A program simulation of the Distributed Logic Memory computer assisted in its development and later permitted verification of programs written for the computer. The existence of a compiler permitted such programs to be written in a convenient, symbolic form. A data multiplexer is developed as a practical application for the Distributed Logic Memory computer structure. The necessary data multiplexer program, which consists of about 100 instructions, is shown. |
| Genre | Thesis/Dissertation |
| Topic | Programming (Electronic computers) |
| Identifier | http://hdl.handle.net/1957/46360 |
