Record Details

Satellite multiplication package for a small digital computer

ScholarsArchive at Oregon State University

Field Value
Title Satellite multiplication package for a small digital computer
Names Chuang, Tsu-Ping Patrick (creator)
Herzog, James H. (advisor)
Date Issued 1972-03-15 (iso8601)
Note Graduation date: 1972
Abstract This thesis is concerned with the design of an external
multiplication package which can be utilized as an I/O device
with a PDP-8/L computer. The multiplier and multiplicand are
assumed to be 12 bit integers. The 24 bit product can be
transferred back to the accumulator of computer 12 bits at a
time. The control pulses for the operation are supplied by
the computer through I/O transfer instructions.
The multiplication package was constructed on three
printed-circuit cards, using only standard TTL IC chips. No
other components were needed. It is simple, inexpensive and
much faster than the method of repeated addition which must
ordinarily be used in the PDP-8. This paper also shows a
division algorithm using the multiplier and trial-and-error.
This method of division is faster than repeated subtraction.
Genre Thesis/Dissertation
Topic Electronic digital computers
Identifier http://hdl.handle.net/1957/45620

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