Record Details
A low ground bounce CMOS off-chip driver design
ScholarsArchive at Oregon State University
| Field | Value |
|---|---|
| Title | A low ground bounce CMOS off-chip driver design |
| Names |
Zheng, Jieyin
(creator) Lu, Shih-Lien (advisor) |
| Date Issued | 1993-08-04 (iso8601) |
| Note | Graduation date: 1994 |
| Abstract | With the advancement of technology, submicron CMOSonly process is available now for Application Specific Integrated Circuits (ASICs). The high integration leads to the need for high pin counts. However voltage supply and ground bounce due to many output drivers switching at the same time is becoming a major problem. In this thesis, a CMOS offchip buffer design which generates ECL logic levels with lower ground bounce noise is described and demonstrated. The technique used in designing this buffer to reduce voltage noise differs from conventional design techniques. Traditionally there are two general methods to reduce ground bounce. One approach tries to reduce the instantaneous current change (di/dt) by increasing (prolonging) the rise and fall time of the signals. The other approach attempts to reduce the parasitic inductance attributed to packaging by using multiple supply pins. Our technique reduces the voltage noise by controlling the instantaneous current change through the reduction of current difference during switching time. Based on this approach, a novel circuit structure is designed. This circuit has a fully symmetrical configuration and is being selfbiased through negative feedback. A current injection technique is also used to increase the stability of the circuit. SPICE simulation of the proposed circuit is performed. Comparison and tradeoffs with other approaches are studied. |
| Genre | Thesis/Dissertation |
| Topic | Emitter-coupled logic circuits -- Design and construction |
| Identifier | http://hdl.handle.net/1957/37203 |
