Record Details
Discrete trap modeling of thin-film transistors
ScholarsArchive at Oregon State University
| Field | Value |
|---|---|
| Title | Discrete trap modeling of thin-film transistors |
| Names |
Yerubandi, Ganesh Chakravarthy
(creator) Wager, John F. (advisor) |
| Date Issued | 2005-10-18T17:30:30Z (iso8601) |
| Internet Media Type | application/pdf |
| Note | Graduation date: 2006 |
| Abstract | A discrete trap model is developed and employed for elucidation of thin-film transistor (TFT) device physics trends. An attractive feature of this model is that only two model parameters are required, the trap energy depth, E[subscript T], and the trap density, N[subscript T]. The most relevant trends occur when E[subscript T] is above the Fermi level. For this case drain current – drain voltage simulations indicate that the drain current decreases with an increase in N[subscript T] and E[subscript T]. The threshold voltage, V[subscript T], extracted from drain current – gate voltage (I[subscript D] – V[[subscript GS]) simulations, is found to be composed of two parts, V[subscript TRAP], the voltage required to fill all the traps and V[subscript ELECTRON], the voltage associated with electrons populating the conduction band. V[subscript T] moves toward a more positive voltage as N[subscript T] and E[subscript T] increase. The inverse subthreshold voltage swing, S, extracted from a log(I[subscript D]) – V[subscript GS] curve, increases as N[subscript T] and E[subscript T] increase. Finally, incremental mobility and average mobility versus gate voltage simulations indicate that the channel mobility decreases with increasing N[subscript T] and E[subscript T]. |
| Genre | Thesis |
| Topic | Thin-film transistor |
| Identifier | http://hdl.handle.net/1957/515 |
